Syllabus
Course Overview
Schedule
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Trainer
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Syllabus
- Using Verdi tool for IP verification debug
- Creating RC file
- Using Message window and source file window for effective tracing
- Learning debug with an industry standard project
- Understanding linker file, dump file for SOC debug
- Using program counter to debug the C test case failure
- Tracing the transactions in SOC hierarchy
- Tracing x-prop
- Debugging setup and hold time issues
- Fixing timing simulation issues
- Understanding UPF updates to fix the issues
Course Overview
Course Overview
A functional verification engineer spends a significant amount of time in debugging during the verification process. This course is designed to cover all major aspects of debug, including module-level verification debug using Verdi and Questasim, GLS x-prop tracing, SoC test failure debug with Tarmac logs, and low-power verification debug.
The program also introduces standard debug practices followed across the industry. Most topics are explained through practical examples, and participants will gain hands-on experience with tools to strengthen their debugging skills.
Schedule
| Course | Physical Design Training |
|---|---|
| Duration | 2 months (6 months for freshers) |
| Course start date | 11th December |
| Schedule | |
| Freshers | Full week course |
| All days except Friday (9AM – 1PM India time). This includes Saturday and Sunday. | |
| Weekdays sessions will be focused on training on CMOS, device fundamentals, Digital Design, Linux OS and TCL scripting for initial 8 weeks. Later 2 months, weekdays will be focused on project hands on labs. | |
| Working professionals | Saturday & Sunday(9AM – 6PM India time. Flexible timings for students attending online from US) |
| 9AM – 1PM (Theory session offered by trainer) | |
| 2PM – 6PM (Lab & tool based session guided by mentor). Students from US will get support in different time. | |
| Students will take the weekday tests and assignments from home. | |
| Students also get support on complete project flow during weekdays as well. | |
| New batch starts | Every 8 Weeks |
| Tools | Synopsys ICC II, RedHawk, Primetime, StarRC, Design Compiler, ICV |
| Mode of training | Classroom training & Online training |
| Online training using live training sessions | |
| Tool Access | Tool access for complete course duration |
| Certificate | Issued based on 50% assignment completion as criteria |
| Batch Size | 20 |
| Assignments | 20 |
| Evaluation tests | 20(evaluation test followed by discussion on same). |
| Placement support | Institute does not give any commitment on job or number of opportunities, however student will be provided with opportunities till he/she gets job. |
| Trainer | 15+ Years of industrial experience |
Demo
Trainer
Experienced Trainer
- The course is delivered by a seasoned professional with 15+ years of industrial experience in VLSI verification and debug. With strong expertise in functional verification, debugging methodologies, and industry-standard tools, the trainer brings real-world knowledge and practical insights to help participants build hands-on skills.
certificate
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- 1-1 Dedicated Mentor Support
- 24/7 Tool Access
- Multiple MOCK Interviews
- Industry Standard Projects
- Resume Preparation