COURSE SCHEDULE (VLSI, EMBEDDED SYSTEMS)

For all courses:

  • 18% GST applicable
  • All Courses offered in
  • Student can join ongoing batch within 2 weeks from course start date, we help cover up the missed sessions.
  • Students joining Design verification, Physical Design, DFT and Custom layout courses, will have option to switch to any other course within 2 months of joining the course with no additional fee.
VLSIguru quality traning affordable fee in Bangalore

Upcoming courses

Courses Start Date Link
Functional verification interview training Adhoc Course Structure
Physical design interview training Adhoc Course Structure

Courses in VLSI Front End domain

Course Start Date Course Duration New Batch starts every
Functional Verification Training for Freshers 15/Nov 28 weeks 5 weeks
Functional Verification Training for Experienced Engineers 25/Nov 22 weeks 5 weeks
System Verilog Training 22/Nov 7 weeks 5 weeks
MTech Internship in VLSI Adhoc 10 months 5 weeks
MTech Internship in Embedded Systems Adhoc 10 months 5 weeks
UVM Training 22/Nov 8 weeks 8 weeks
RTL Design and Verification Training Adhoc 24 weeks 5 weeks
FPGA Design and Verification Training 15/Nov 24 weeks 5 weeks
Verilog Training 10/Nov 8 weeks 5 weeks
VHDL Training Adhoc 5 weeks Adhoc

Courses in VLSI Backend DOMAIN

Course Start Date Course Duration New Batch starts every
Physical Design Training 16/Nov 24 Weeks 8 weeks
RedHawk (Power Integrity & IR Drop Analysis) Training Adhoc 5 Weeks
Synthesis and STA Training Adhoc 12 Weeks 8 weeks
DFT Training 15/Nov 24 Weeks 8 weeks
Custom Layout & Physical Verification Training 16/Nov 24 Weeks 8 weeks

Courses in Embedded Systems

Course Start Date Course Duration New Batch starts every
Embedded Systems Training 15/Nov 18 Weeks 9 weeks

Courses on SOC & Standard Protocols

  • Ad Hoc below refers to, courses where we do not get frequent requests, and are offered only when more than 5 students register for the course.
Course Start Date Course Duration New Batch starts every
ARM Training 02/Nov 6 Weeks Adhoc
DDR Protocol Adhoc 6 Weeks Adhoc
PCIe Gen5 Protocol Adhoc 6 Weeks 16 weeks
USB3.2 Protocol Adhoc 6 Weeks 16 weeks
Gate Level Simulations (GLS) Adhoc 3 Weeks 16 weeks
Low Power Verification Adhoc 3 Weeks Adhoc
USB2.0 Protocol and USB2.0 Core Verification Adhoc 7 Weeks Adhoc
AMBA Protocol and UVC Development Adhoc 6 Weeks 12 weeks
AMBA CHI Adhoc 6 Weeks 6 weeks
ACE Protocol Adhoc 6 Weeks 5 weeks
SoC Design & Verification Adhoc 6 Weeks Adhoc

Courses on Scripting Languages

Course Start Date Course Duration New Batch starts every
PERL adhoc 5 Weeks 10 weeks
Python adhoc 5 Weeks 10 weeks
TCL Adhoc 6 Weeks 10 weeks
Shell Adhoc 4 Weeks 10 weeks

Contact us for more details on VLSI Training course structure

Course Registration