AHB-PROTOCAL-PPT

SESSION#1(5/APR) Revision: o ASIC FLow o ASIC vs FPGA o Front End FLow – Design – RTL – Functional Verification or RTL Verification – If some issues are found here in the RTL it is easy to fix them. – TestBench o Synthesis – Input : RTL – Output : Netlist Doubts: Notes: o TestBench: […]

22/FEB Revision : we have created test, env inside test, agent inside env. top uvm_root test env agent driver we have discussed about uvm_root. singleton instance it is responsible for phase handling can read command line arguements phase concept task run_phase(uvm_phase phase); phase.raise_objection #100; phase.drop objection endtask -set_drain_time – verbosity uvm_printer types : (policy classes) […]