Advanced Physical Design Training

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Advanced Physical Design Training is a 5-month course designed for working professionals to gain in-depth knowledge of Physical Design flow Netlist to GDSII, including all stages at the 14nm technology node. The course includes hands-on training using Synopsys and Cadence Innovus tools with 100% Placement support and 24*7 Tool Access.

4.6 Star (985 rating) 1,297 (Student Enrolled)

Trainer
Multiple Experienced Trainers

Syllabus

Course Overview

Projects

Schedule

Demo

FAQs

Trainer

Certificate

Syllabus

Advanced Physical design course syllabus (Duration: 5 months)

EDA Tools Used in Physical Design Flow

PD Flow Stage	Synopsys Tool	Cadence Tool
RTL to Gate Synthesis	Design Compiler (DC)	Genus
Floorplanning & Placement	IC Compiler II (ICC2)	Innovus
Power Planning	ICC2 / PrimePower	Innovus / Voltus
Clock Tree Synthesis (CTS)	ICC2	Innovus
Routing (Global + Detailed)	ICC2	Innovus
Parasitic Extraction (PEX)	StarRC	Quantus QRC
Timing Analysis (STA)	PrimeTime	Tempus
Signal Integrity (SI)	PrimeTime SI / StarRC	Tempus SI / Quantus QRC
Power Integrity (IR/EM)	RedHawk-SC (via ANSYS)	Voltus
Formal Equivalence Checking	Formality	Conformal
Physical Verification (DRC/LVS/ERC)	IC Validator (ICV)	Pegasus / PVS
GDSII Generation	ICC2	Innovus

Synthesis

Basics of Synthesis
High Level Synthesis Flow
Reading of Verilog RTL File
Target and Link Libraries
Resolving References with Link Libraries
Reading hierarchical Designs
Reading ddc design
Analyse & Elaborate Commands
Constraining and Compiling RTL
Post Synthesis Output Data

Timing Constraints

Constraining Register to Register Paths
Constraining Inputs Paths
Constraining Outputs Paths
Virtual Clock
Load Budgeting
Default Path Groups
Creating User-defined Path Groups
Prioritizing Path Groups
Timing Reports
Analyzing Timing Reports
Defining a Clock with additional options
Input Delay with additional options
Output Delay with additional options
Pre-CTS versus Post CTS Clock Latencies
Independent IO Latencies
Output Delay with Network Latency
Output Delay with Source Latency
Different IO versus Internal Latencies
IO Clock Latencies
Handling Different IO Vs Internal Latencies
Virtual External Clock Latencies
Included External Clock Latencies
Multiple Synchronous Clocks
Multiple Clocks Input Delay
Maximum Internal Input Delay
Multiple Clock Output Delay
Maximum Internal Output Delay
Inter Clock Uncertainty
Generated Clocks
Mutual Exclusive Synchronous Clocks
Logically Exclusive Clocks
Multiple Clocks per Register
Cross Talk Analysis
Asynchronous Clocks
Multi Cycle Paths and Constraints

UPF

High Level Multi-Voltage Design Concepts
Supplies and Power Domains
Power Ports and Nets
Level Shifters
Power States and PS Table

NDM Libraries

IC Compiler II Library Manager
ICC Compiler II NDM Cell Library
Cell Library Characteristics
Library Manager Flow
Tech Only NDM Library
Technology-Only Library Flow
Technology File
Read TLU+ Files
Tech Library Preparation

Initial Design Setup

Top Level, Sub-System Level and Block Level Design Setup
Set up initial Design Implementation
Loading Netlist from Synthesis
Setting Path to dotlibs, LEFs, DEFs (if needed), Technology Files, SDC files
Flow Setup and Design Setup
Loop-back to Synthesis for Correlation issues correction

FloorPlanning

Initial Floorplanning settings
Define Pad Instances (Physical Cells)
Pad Instance co-ordinates
Start Floorplaning
Core Die Size setting
Floorplanning of Pad Instances
Pad Filler Insertion
Define Pad Ring Power Grid
Macro Instance constraints
Macro Instance Array creation
Macro Instance Orientation
Anchor based and Relative Placement of Macro Instances
Macro Instance-Channel settings
Macro Instance placement – Manual
Congestion probability around Macro Instances
Defining Placement Blockages

Placement

Running placement
Defining placement strategies
In Place Optimization
Hierarchical Placement
Relative Placement
Congestion analysis and reduction
Macro placement changes to reduce congestion
Standard Cell Placement Constraints
Halo creation for instances
Congestion Analysis with Standard Cell placement
Local Congestion Reduction
Density Screen and Placement Blockage for Standard Cells
Congestion Aware Placement
Re-Check Macro Placement for better Congestion relief
Create Balanced Buffer Trees for High Fanout Net

Power Planning

Defining Power Structure
Logical Power/Ground Connections
Setting Power Network Constraints
Create and Analyze Power Structure
Change Power Constraints and Re-Createto meet IR requirements
Power Ground Pin connection and create Power Rails
Power Network Checks for IR and Resistance
Placement Blockage for Power Network
Incremental Placement

Scan Chain RE-Ordering and RE-Partitioning

Re-Order Scan connectivity within Chain
Re-Partition Scan connectivity across Chains
SCANDEF file based Scan Chain Re-Ordering

Global Routing

Congestion checks for Overflow again
RC extraction for Net Parasitics
Check Timing for Max Analysis
Run Timing/Congestion aware Placement
Logic Re-Structuring for Placement and Timing

Clock Tree Synthesis

Check Pre-CTS timing based on Global Routing and Detailed Placement
Setting Clock Constraints such as Target Skew Target Insertion Delay
Clock Root Attributes as Stop, Float and Exclude Pins
Building for Generated and Gated Clocks
Don’t Touch attribute on existing Clock Tree structure
Defining Clock Buffers and Inverters.
Set Clock Tree Timing DRCs.
Non-Default Clock Routing rules setting
Perform Clock Tree Synthesis and Clock Tree Optimization
Reduce Hold Violations in Data paths and Scan Paths
Clock Tree Building/Optimization for Multiple modes and Multiple PVT corners
Synchronous Clock Balancing
Cross-Clock Delay Balancing
Logical Hierarchy aware CTS
Max and Min Analysis and subsequent Optimization
Fixing Violations
CTS Optimization across other modes and PVT corners (MMMC)
Skew and Insertion Delay checks
Checking Crosstalk on Clock Network

Detailed Routing

Pre-Route check points
Routing fundamentals
Global Route
Detail Routing
Track Assignment and Route
Refining Detailed Route
Over the Macro routing
Non-Preferred Routing direction
Clock Net Routing
Initial Data path routing
Redundant VIA insertion setting
Post Detailed Route Optimization
Fixing DRC Violations
Post Detailed Route Delay Calculation Algorithms
Crosstalk Delay and Noise Analysis and Fix

Power Analysis (Static and Dynamic)

Check Leakage Power Dissipation
VT Cell swap for power and timing trade-off
Analyzing Dynamic Power Dissipation based on GAF, SAIF, VCD
Reduce Dynamic power
Meet Total Power target

Engineering Change Order Flow (ECO)

Functional ECO
Timing ECO
Metal Only ECO using Spare Cells for base frozen designs

Multiple Industry standard Projects

Projects covering detailed flow from Input files, floorplan, power planning, placement, CTS, Routing, SPEF extraction, STA, and Physical verification.
- One project completely guided by the trainer
- Other project done by student with trainer guidance
Project based on multi voltage domain.

Design For Manufacturability

Antenna Rules and Fixes
Critical Area Analysis
Wire Spreading and widening
Setting minimum metal jog length
Filler Cell Insertion
Metal Fill
Timing Checks after Metal Fill
Parasitic Extraction for SignOff timing analysis
Export Netlist
Export GDSII

Course Overview

Projects

Schedule

Course	Advanced Physical Design Training
Duration	5 months
Course start date	16/Nov
Schedule
	9AM – 1PM (Theory session offered by trainer)
	2PM – 6PM (Lab & tool based session guided by mentor). Students from US will get support in different time.
Tools	SYNOPSYS, CADENCE {Synopsys ICC II, RedHawk, Primetime, StarRC, Design Compiler, ICV}
Mode of training	Classroom training & Live Online training
Tool Access	24×7 Tool access for complete course duration
Certificate	Certificate of course completion issued
Batch Size	20
Assignments	20
Trainer	15+ Years of industrial experience