1-1 training Highlights
- 150 hours of 1-1 training at student flexible timings
- Support with office work debug (for working professionals)
- Complete guided project support, and 24x7 tool access for hands on practice
- Course content can be customized(topics added and removed) as per student requirements
- Trainer support outside teaching hours.
- Regular mock interviews and assessment tests for performance tracking
dft
Course content - Hourly breakup
| Topic | Duration(Hours) |
|---|---|
| Number systems, Radix conversion | 2 |
| Combinational logic | 3 |
| Sequential logic | 3 |
| Total | 8 |
| Topic | Duration(Hours) |
|---|---|
| “Unix Directory commands , file comaparing commands” | 2 |
| Filter and data manipulation Commands | 2 |
| “File permission Commands and micellaneous Commands” | 2 |
| Unix Environmental Variables | 2 |
| Total | 8 |
| Topic | Duration(Hours) |
|---|---|
| TCL Basic Commands Operators, Special variables , loops | 3 |
| TCL List , string and arrays | 2 |
| TCL dictionaries and its example programs | 2 |
| TCL procedure and its example programs | 2 |
| TCL regular expression and example programs | 2 |
| Total | 11 |
| Topic | Duration(Hours) |
|---|---|
| Introduction to Verilog, Basic Synax, Operators | 2 |
| Combinational logic Design | 3 |
| Sequential logic Design | 3 |
| Total | 8 |
| Topic | Duration(Hours) |
|---|---|
| Scan Insertion and its need, Scan chain operation | 2 |
| Scan Methodologies and Scan Flow | 3 |
| Scan Insertion DRCs | 2 |
| Edge mixing and Domain mixing | 2 |
| Scan Insertion Labs | 3 |
| Total | 12 |
| Topic | Duration(Hours) |
|---|---|
| Scan Compression and its need | 2 |
| Decompressor, Compressor and Masking Logic | 3 |
| EDT bypass and 1-hot decoding | 2 |
| EDT Labs | 3 |
| Total | 10 |
| Topic | Duration(Hours) |
|---|---|
| ATPG Need, Fault Simulation | 2 |
| Fault Classes | 1 |
| Fault Categories, Fault Model Overview | 1 |
| Stuck at Fault model | 1 |
| Transition Delay Fault model | 1 |
| IDDQ fault model | 1 |
| Different Types of Patterns | 1 |
| On-chip clock controller (OCC) | 1 |
| ATPG Labs (SA, TDF, IDDQ) | 4+2+2=8 |
| Total | 17 |
| Topic | Duration(Hours) |
|---|---|
| Simulation and its need | 1 |
| Simulation Labs | 2 |
| Simulation Mismatch Debug Labs | 2 |
| Total | 5 |
| Topic | Duration(Hours) |
|---|---|
| JTAG Architecture | 1 |
| JTAG Controller (FSM) | 1 |
| Comparision between IEEE 1149.1 STD and IEEE 1687 STD | 1 |
| Boundary Scan | 2 |
| Total | 5 |
| Topic | Duration(Hours) |
|---|---|
| Memory Basics | 2 |
| Memory Faults | 2 |
| Memory Algorithms | 2 |
| MBIST Architecture | 1 |
| Total | 5 |
| Topic | Duration(Hours) |
|---|---|
| IJTAG and MBIST insertion for COREA | 2 |
| EDT and OCC insertion for COREA | 1 |
| Wrapper insertion, Scan Insertion, Graybox generation for COREA | 1 |
| ATPG and Simulations for COREA | 1 |
| IJTAG and MBIST insertion, EDT OCC insertion for COREB | 1 |
| Wrapper insertion, Scan Insertion, Graybox generation for COREB | 1 |
| ATPG and Simulations for COREB | 1 |
| Total | 9 |
| Topic | Duration(Hours) |
|---|---|
| PLL handling, pin-mux logic | 1 |
| IJTAG,MBIST insertion | 2 |
| EDT OCC insertion, Scan insertion, ATPG | 2 |
| Total | 5 |